-------------------------------------------------------------------------------- -- Company: FSU-FAMU -- Engineer: YOUR_NAME -- Create Date: TODAY -- Design Name: f5direct -- Project Name: lab 5 -- Target Device: EP2C35F672C6 -- Tool versions: Quartus II 9.1 -- Description: This is a Module for the FIR lab for the book DSP with FPGAs. -- F5 coefficients: f[0] = f[10] = 3, f[2] = f[8] = -25=-(3*8+1), -- f[4] = f[6] =150=25*3*2, and f[5] = 256 -- Compute the half band filter F5 in direct form. -- -- Dependencies: None -- -- Resources used: -- Total Number LEs: -- Number of 9x9 Mults: -- Bits of M4Ks: 0 -- Maximum Delay is ns => MHz -------------------------------------------------------------------------------- PACKAGE N_bit_int IS -- User define Types, Objects, Attributes SUBTYPE S16 IS INTEGER RANGE -2**15 TO 2**15-1; SUBTYPE S26 IS INTEGER RANGE -2**25 TO 2**25-1; TYPE ARRAY_S26 is array (0 to 10) of S26; END N_bit_int; LIBRARY work; USE work.N_bit_int.ALL; LIBRARY ieee; -- Using predefined Packages USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; ENTITY f5direct IS ------> Interface PORT (clk : IN STD_LOGIC; x : IN S16; f5 : OUT S26 := 0); END; ARCHITECTURE fpga OF f5direct IS SIGNAL r : ARRAY_S26 := (0,0,0,0,0,0,0,0,0,0,0); -- taped delay line array of words BEGIN P1: PROCESS (clk, r, x) ------> Behavioral Style BEGIN r(0) <= x; IF RISING_EDGE(clk) THEN -- FIR filter in direct form FOR k IN 0 TO 9 LOOP -- TAP delay line shift one r(k+1) <= r(k); END LOOP; f5 <= 3*r(0) - 25*r(2) + 150*r(4) + 256*r(5) + 150*r(6) - 25*r(8) + 3*r(10); END IF; END PROCESS; END fpga;