Model { Name "lab1" Version 7.3 MdlSubVersion 0 GraphicalInterface { NumRootInports 0 NumRootOutports 0 ParameterArgumentNames "" ComputedModelVersion "1.236" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "ibm-5348_P100-1997" SaveDefaultBlockParams on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" InitFcn "%% DSPBuilder Start\nalt_dspbuilder_update_model(bdroot)\n%% DSPBuilder End\n" Created "Thu Aug 05 16:35:41 2004" Creator "umb" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "umb" ModifiedDateFormat "%" LastModifiedDate "Tue Jan 19 13:48:59 2010" RTWModifiedTimeStamp 0 ModelVersionFormat "1.%" ConfigurationManager "None" SampleTimeColors off SampleTimeAnnotations off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes on ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowSignalResolutionIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off SimulationMode "normal" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on CovModelRefEnable "Off" CovExternalEMLEnable off ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.6.0" Array { Type "Handle" Dimension 8 Simulink.SolverCC { $ObjectID 2 Version "1.6.0" StartTime "0.0" StopTime "5*10^3" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ZcThreshold "auto" ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "SingleTasking" Solver "FixedStepDiscrete" SolverName "FixedStepDiscrete" ShapePreserveControl "DisableAll" ZeroCrossControl "UseLocalSettings" ZeroCrossAlgorithm "Nonadaptive" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" InsertRTBMode "Whenever possible" SignalSizeVariationType "Allow only fixed size" } Simulink.DataIOCC { $ObjectID 3 Version "1.6.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveCompleteFinalSimState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on InspectSignalLogs off SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "sigsOut" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Version "1.6.0" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off InlineInvariantSignals on OptimizeBlockIOStorage on BufferReuse on EnhancedBackFolding off StrengthReduction off EnforceIntegerDowncast on ExpressionFolding on EnableMemcpy on MemcpyThreshold 64 PassReuseOutputArgsAs "Structure reference" ExpressionDepthLimit 2147483647 FoldNonRolledExpr on LocalBlockOutputs on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off EfficientMapNaN2IntZero on OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on SimCompilerOptimization "Off" AccelVerboseBuild off } Simulink.DebuggingCC { $ObjectID 5 Version "1.6.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" SignalRangeChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" SaveWithDisabledLinksMsg "warning" SaveWithParameterizedLinksMsg "none" CheckSSInitialOutputMsg on UnderspecifiedInitializationDetection "Classic" MergeDetectMultiDrivingBlocksExec "none" CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "TryResolveAllWithWarning" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" SolverPrmCheckMsg "none" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "warning" MultiTaskCondExecSysMsg "none" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" ParameterTunabilityLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StateNameClashWarn "warning" StrictBusMsg "None" LoggingUnavailableSignals "error" BlockIODiagnostic "none" } Simulink.HardwareCC { $ObjectID 6 Version "1.6.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown on ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.6.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.SFSimCC { $ObjectID 8 Version "1.6.0" SFSimEnableDebug on SFSimOverflowDetection on SFSimEcho on SimBlas on SimUseLocalCustomCode off SimBuildMode "sf_incremental_build" } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 9 Version "1.6.0" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off RTWUseLocalCustomCode off RTWUseSimCustomCode off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime on GenerateTraceInfo off GenerateTraceReport off GenerateTraceReportSl off GenerateTraceReportSf off GenerateTraceReportEml off GenerateCodeInfo off RTWCompilerOptimization "Off" CheckMdlBeforeBuild "Off" Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 10 Version "1.6.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IgnoreTestpoints off IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off UseSimReservedNames off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 11 Version "1.6.0" TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" TargetFunctionLibrary "ANSI_C" UtilityFuncGeneration "Auto" ERTMultiwordTypeDef "System defined" ERTMultiwordLength 256 MultiwordLength 2048 GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant off ParMdlRefBuildCompliant on CompOptLevelCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off ERTFirstTimeCompliant off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging off MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on EnableShiftOperators on ParenthesesLevel "Nominal" PortableWordSizes off ModelStepFunctionPrototypeControlCompliant off CPPClassGenCompliant off AutosarCompliant off UseMalloc off ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" ExtModeIntrfLevel "Level1" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" CurrentDlgPage "Solver" ConfigPrmDlgPosition " [ 70, 232, 950, 862 ] " } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on BlockRotation 0 BlockMirror off } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Helvetica" FontSize 10 FontWeight "normal" FontAngle "normal" UseDisplayTextAsClickCallback off } LineDefaults { FontName "Helvetica" FontSize 9 FontWeight "normal" FontAngle "normal" } BlockParameterDefaults { Block { BlockType Constant Value "1" VectorParams1D on SamplingMode "Sample based" OutMin "[]" OutMax "[]" OutDataTypeMode "Inherit from 'Constant value'" OutDataType "fixdt(1,16,0)" ConRadixGroup "Use specified scaling" OutScaling "[]" OutDataTypeStr "Inherit: Inherit from 'Constant value'" LockScale off SampleTime "inf" FramePeriod "inf" } Block { BlockType Scope ModelBased off TickLabels "OneTimeTick" ZoomMode "on" Grid "on" TimeRange "auto" YMin "-5" YMax "5" SaveToWorkspace off SaveName "ScopeData" LimitDataPoints on MaxDataPoints "5000" Decimation "1" SampleInput off SampleTime "-1" } Block { BlockType Terminator } } System { Name "lab1" Location [140, 155, 1204, 713] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "104" ReportName "simulink-default.rpt" Block { BlockType Reference Name "AltBus" Ports [1, 1] Position [350, 122, 415, 138] BlockMirror on ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/AltBus" SourceType "AltBus AlteraBlockset" BusType "Unsigned Integer" bwl "29" bwr "0" saturate off floatingPointInput on floatingPointOutput on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_AltBu" "s.fixedpointlog" } Block { BlockType Reference Name "Binary To Seven Segments" Ports [1, 1] Position [615, 415, 685, 465] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Binary To Seven Segments" SourceType "Binary To Seven Segment AlteraBlockset" pipeline_display "0" } Block { BlockType Reference Name "Bus Concatenation" Ports [2, 1] Position [215, 167, 275, 278] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Bus Concatenation" SourceType "Bus Concatenate AlteraBlockset" isSigned off awidth "13+8" bwidth "8" pipeline_display "0" } Block { BlockType Reference Name "Bus Conversion" Ports [1, 1] Position [490, 209, 565, 231] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Bus Conversion" SourceType "Bus Conversion AlteraBlockset" BusType "Unsigned Integer" ibwl "29" ibwr "1" bwl "7" bwr "1" bitToConnectToOutputLSB "10" round off saturate off pipeline_display "0" Port { PortNumber 1 Name "triangle MSBs" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Bus Conversion1" Ports [1, 1] Position [490, 320, 565, 340] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Bus Conversion" SourceType "Bus Conversion AlteraBlockset" BusType "Unsigned Integer" ibwl "29" ibwr "1" bwl "14" bwr "1" bitToConnectToOutputLSB "3" round off saturate off pipeline_display "0" } Block { BlockType Reference Name "Bus Conversion2" Ports [1, 1] Position [485, 428, 565, 452] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Bus Conversion" SourceType "Bus Conversion AlteraBlockset" BusType "Unsigned Integer" ibwl "29" ibwr "1" bwl "4" bwr "1" bitToConnectToOutputLSB "25" round off saturate off pipeline_display "0" } Block { BlockType Reference Name "Clock" Ports [] Position [294, 475, 344, 493] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Clock" SourceType "BaseClock AlteraBlockset" ClockPeriod "10" ClockPeriodUnit "ns" SampleTime "1" ResetLatency "0" ResetRegisterCascadeDepth "0" SimulationStartCycle "5" PhaseOffset "0" Reset "aclr" ResetType "Active Low" Export off } Block { BlockType Constant Name "Constant1" Position [30, 235, 60, 265] Value "32" OutDataType "fixdt(1, 16)" OutScaling "2^0" } Block { BlockType Constant Name "Constant2" Position [675, 255, 705, 285] Value "0" OutDataType "fixdt(1, 16)" OutScaling "2^0" } Block { BlockType Reference Name "Cyclone II EP2C35 DSP \nDevelopment Board" Ports [] Position [270, 380, 368, 433] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/Cyclone II EP2C35 DSP Development Board" SourceType "CycloneIIEP2C35 Configuration AlteraBlockSet" ClockPinIn "Pin_N2" GlobalResetPin "Pin_A14" device "EP2C35F672C6" } Block { BlockType Reference Name "D2A_1 \n14 Bit Unsigned" Ports [1, 1] Position [905, 285, 950, 325] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/D2A_1 14 Bit Unsigned" SourceType "CycloneIIEP2C35 D2A_1 14 Bit Unsigned AlteraBlockSet" iofile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_D2A%5F" "1+%0A14+Bit+Unsigned.capture" externalType "Inferred" location "Pin_AB1,Pin_AA1,Pin_AE3,Pin_AD3,Pin_U3,Pin_T2,Pin_Y4,Pin_AA5,Pin_V5,Pin_V6,Pin_P3,Pin_U7,Pin_R5" ",Pin_P6" } Block { BlockType Reference Name "Delay" Ports [1, 1] Position [390, 180, 430, 230] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Delay" SourceType "Delay AlteraBlockset" pipeline "1" pipeline_display "1" ClockPhase "1" use_ena off use_sclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Delay" ".fixedpointlog" use_init off reset_value "1" Port { PortNumber 1 Name "triangle 29 bits" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "Delay0" Ports [1, 1] Position [630, 305, 670, 355] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Delay" SourceType "Delay AlteraBlockset" pipeline "1" pipeline_display "1" ClockPhase "1" use_ena off use_sclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Delay" "0.fixedpointlog" use_init off reset_value "1" } Block { BlockType Reference Name "Delay1" Ports [1, 1] Position [745, 415, 785, 465] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Delay" SourceType "Delay AlteraBlockset" pipeline "1" pipeline_display "1" ClockPhase "1" use_ena off use_sclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Delay" "1.fixedpointlog" use_init off reset_value "1" } Block { BlockType Reference Name "Delay2" Ports [1, 1] Position [745, 340, 785, 390] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Delay" SourceType "Delay AlteraBlockset" pipeline "1" pipeline_display "1" ClockPhase "1" use_ena off use_sclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Delay" "2.fixedpointlog" use_init off reset_value "1" } Block { BlockType Reference Name "Dip Switch" Ports [1, 1] Position [90, 233, 165, 267] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/Dip Switch" SourceType "CycloneIIEP2C35 Dip Switch AlteraBlockSet" iofile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Dip+Sw" "itch.salt" externalType "Inferred" SpecifyClock off location "Pin_AC13,Pin_A19,Pin_C21,Pin_C23,Pin_AF4,Pin_AC20,Pin_AE18,Pin_AE19" } Block { BlockType Reference Name "LED0" Ports [1, 1] Position [895, 239, 940, 251] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/LED0" SourceType "CycloneIIEP2C35 LED0 AlteraBlockSet" iofile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_LED0.c" "apture" externalType "Inferred" location "Pin_E5" } Block { BlockType Reference Name "LUT" Ports [1, 1] Position [615, 153, 705, 237] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/LUT" SourceType "LUT AlteraBlockset" addr_width "7" BusType "Unsigned Integer" bwl "14" bwr "0" init_array "floor((2^13-1)*sin([0:127]*2.0*pi/128)+2^13)" allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_LUT.f" "ixedpointlog" use_ena off reg_data off use_lpm on reg_addr on ram_type "AUTO" pipeline_display "1" Port { PortNumber 1 Name "sine unsigned" RTWStorageClass "Auto" DataLoggingNameMode "SignalName" } } Block { BlockType Reference Name "MSBs" Ports [0, 1] Position [75, 186, 125, 204] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Constant" SourceType "Constant AlteraBlockset" mask_cst "0" BusType "Unsigned Integer" bwl "13" bwr "0" roundMode "Truncate" satMode "Wrap" SpecifyClock off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_MSBs." "fixedpointlog" } Block { BlockType Reference Name "Multiplexer" Ports [3, 1] Position [820, 265, 870, 345] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Multiplexer" SourceType "Multiplexer AlteraBlockset" numInputs "2" pipeline "0" oneHot off pipeline_display "0" use_ena off use_aclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Multi" "plexer.fixedpointlog" } Block { BlockType Reference Name "Parallel Adder Subtractor0" Ports [2, 1] Position [305, 167, 340, 243] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Parallel Adder Subtractor" SourceType "ParallelAdder AlteraBlockset" number_of_inputs "2" direction "+" use_pipeline off pipeline_display "0" phase_selection "1" use_ena off use_aclr off allowFloatingPointOverride on logOutputs off logFile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Paral" "lel+Adder+Subtractor0.fixedpointlog" } Block { BlockType Reference Name "Resource Usage" Ports [] Position [166, 25, 255, 78] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Resource Usage" SourceType "Resource Usage AlteraBlockset" logic " < 1 %% " memory " < 1 %% " dsp " 0 %% " memoryLable "RAM" dspLable "Multiplier" } Block { BlockType Reference Name "SW2" Ports [1, 1] Position [735, 247, 775, 293] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/SW2" SourceType "CycloneIIEP2C35 SW2 AlteraBlockSet" iofile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_SW2.sa" "lt" externalType "Inferred" SpecifyClock off location "Pin_AE14" } Block { BlockType Scope Name "Scope" Ports [3] Position [895, 83, 940, 207] Floating off Location [659, 126, 1478, 659] Open off NumInputPorts "3" ZoomMode "xonly" List { ListType AxesTitles axes1 "%" axes2 "%" axes3 "%" } YMin "-1~-8601.6~-1" YMax "1~-7782.4~1" DataFormat "StructureWithTime" LimitDataPoints off SampleTime "0" } Block { BlockType Reference Name "Seven Segment \nDisplay 0" Ports [1, 1] Position [825, 414, 865, 466] ForegroundColor "blue" SourceBlock "Cyclone_II_EP2C35_alteradspbuilder2/Seven Segment Display 0" SourceType "CycloneIIEP2C35 Seven Segment Display 0 AlteraBlockSet" iofile "C:\\Documents and Settings\\Uwe\\tex\\PRO\\CCLI\\AlteraLab2010\\LabIntroDoc\\tb_lab1\\lab1_Seven+" "Segment+%0ADisplay+0.capture" externalType "Inferred" location "Pin_Y21,Pin_T7,Pin_AB23,Pin_Y5,Pin_E1,Pin_U1,Pin_W21,Pin_V3" } Block { BlockType Reference Name "SignalCompiler" Ports [] Position [39, 28, 108, 75] ForegroundColor "blue" SourceBlock "allblocks_alteradspbuilder2/Signal Compiler" SourceType "Signal Compiler AlteraBlockset" DeviceFamily "Cyclone II" DeviceName "EP2C35F672C6" EnableSignalTap on SignalTapDepth "512" UseBoardBlock off StpUseDefaultClock on StpClock "Clock" ExportDir "C:\\Documents and Settings\\umb\\My Documents" } Block { BlockType Terminator Name "Terminator1" Position [960, 235, 980, 255] ShowName off } Block { BlockType Terminator Name "Terminator2" Position [975, 295, 995, 315] ShowName off } Block { BlockType Terminator Name "Terminator26" Position [895, 430, 915, 450] ShowName off } Line { SrcBlock "Parallel Adder Subtractor0" SrcPort 1 DstBlock "Delay" DstPort 1 } Line { SrcBlock "Bus Conversion2" SrcPort 1 DstBlock "Binary To Seven Segments" DstPort 1 } Line { Name "sine unsigned" Labels [0, 0] SrcBlock "LUT" SrcPort 1 Points [10, 0; 0, 0] Branch { Labels [1, 1] Points [0, 0; 125, 0; 0, -10] DstBlock "Scope" DstPort 3 } Branch { Points [0, 170] DstBlock "Delay2" DstPort 1 } } Line { SrcBlock "Binary To Seven Segments" SrcPort 1 DstBlock "Delay1" DstPort 1 } Line { SrcBlock "Delay1" SrcPort 1 DstBlock "Seven Segment \nDisplay 0" DstPort 1 } Line { SrcBlock "MSBs" SrcPort 1 DstBlock "Bus Concatenation" DstPort 1 } Line { SrcBlock "Bus Concatenation" SrcPort 1 DstBlock "Parallel Adder Subtractor0" DstPort 2 } Line { Name "triangle MSBs" Labels [0, 0] SrcBlock "Bus Conversion" SrcPort 1 Points [20, 0; 0, -25] Branch { Labels [2, 0] Points [0, -50] DstBlock "Scope" DstPort 2 } Branch { DstBlock "LUT" DstPort 1 } } Line { SrcBlock "SW2" SrcPort 1 Points [0, 10; 15, 0] Branch { DstBlock "Multiplexer" DstPort 1 } Branch { Points [0, -35] DstBlock "LED0" DstPort 1 } } Line { SrcBlock "Bus Conversion1" SrcPort 1 DstBlock "Delay0" DstPort 1 } Line { SrcBlock "Delay0" SrcPort 1 Points [85, 0; 0, -25] DstBlock "Multiplexer" DstPort 2 } Line { SrcBlock "Multiplexer" SrcPort 1 DstBlock "D2A_1 \n14 Bit Unsigned" DstPort 1 } Line { SrcBlock "Seven Segment \nDisplay 0" SrcPort 1 DstBlock "Terminator26" DstPort 1 } Line { SrcBlock "Delay2" SrcPort 1 Points [5, 0; 0, -35] DstBlock "Multiplexer" DstPort 3 } Line { SrcBlock "AltBus" SrcPort 1 Points [-55, 0] DstBlock "Parallel Adder Subtractor0" DstPort 1 } Line { SrcBlock "Dip Switch" SrcPort 1 DstBlock "Bus Concatenation" DstPort 2 } Line { SrcBlock "Constant1" SrcPort 1 DstBlock "Dip Switch" DstPort 1 } Line { Name "triangle 29 bits" Labels [0, 0] SrcBlock "Delay" SrcPort 1 Points [15, 0; 0, 15] Branch { Points [0, 0] Branch { Points [0, -90] Branch { Labels [1, 0] Points [0, -25] DstBlock "Scope" DstPort 1 } Branch { DstBlock "AltBus" DstPort 1 } } Branch { DstBlock "Bus Conversion" DstPort 1 } } Branch { Points [0, 110; 0, 0] Branch { DstBlock "Bus Conversion1" DstPort 1 } Branch { Points [0, 110] DstBlock "Bus Conversion2" DstPort 1 } } } Line { SrcBlock "LED0" SrcPort 1 DstBlock "Terminator1" DstPort 1 } Line { SrcBlock "D2A_1 \n14 Bit Unsigned" SrcPort 1 DstBlock "Terminator2" DstPort 1 } Line { SrcBlock "Constant2" SrcPort 1 DstBlock "SW2" DstPort 1 } Annotation { Name "Lab 1: Introduction to Simulink " Position [597, 36] ForegroundColor "blue" FontName "Arial" FontSize 36 } Annotation { Name "Design name: Lab1\nDesigner: YourName\nDate:\nVersion:" Position [85, 415] HorizontalAlignment "left" DropShadow on TeXMode "on" FontName "Arial" FontWeight "bold" } } }