FROM:              Dr. U. Meyer-Baese

SUBJECT:            C2H on DE2 Tutorial

 

Here is a short tutorial how to run C2H on the popular Altera/TERASIC DE2 boards:

 

1) Go through the SOPC and then the SDRAM tutorial that teaches you how to set up a NIOS II system that includes (green) LEDs, switches and the SDRAM interface. It also includes instruction how to instantiate a PLL into your NIOS system to produce the -3 ns phase shift for your SDRAM clock. VHDL and Verilog tutorials for the SDRAM are available at:

http://www.altera.com/education/univ/materials/manual/unv-lab-manual.html

 

2) Next step would be to add a timer to your system to perform the elapsed time measurements. Otherwise you can not really compare the system with/without C2H. We call the timer sys_clk_timer and the parameter are as follows:

After you have added the timer to your design, you can generate the new Nios II system, compile it, and download it to the DE2 board.

 

3) Now we start ISE to run an example program – the Altera Monitor Program can not be used for C2H. The Nios II C2H User Guide in Chapter 2 includes a Getting Started Tutorial design that we can use to test our DE2 system. This is a DMA copy function optimization that demonstrates the C2H improvements. It includes detailed instruction how to set up the ISE software project and how the C2H compiler can be utilized. We use the same code just add LEDs displays to show that the DE2 is really working. Make sure that the base address from SOPC is used in your software project such that the LEDs light up.

 

The complete project for Quartus/ISE 8.1 including the software can be downloaded here.

If you run through the software only project it will produce a result like this.

Here are some runtime measurements for the DE2 without C2H:

 

Nios II/e (debug)

Nios II/e (Release)

Nios II/s (release)

Nios II/f (release)

318770 ms

88720 ms

19900 ms

39220 ms

You need to make change in the SOPC builder to generate this different system. Use the default setting and let interrupt table be placed in the SDRAM.

 

Here are some runtime measurements for the DE2 with C2H:

 

Nios II/e (debug)

Nios II/e (Release)

Nios II/s (release)

Nios II/f (release)

Time

19520 ms

20570 ms

10950 ms

10910

Speed-Up:

16.3

4.31

1.81

3.5

Remember that you need to download the SOF file with the new Nios with accelerator to the DE2 before you can measure the execution time. You need to be patient: the C2H compiler need to do a lot and needs some time to complete.

 

If you encounter problems with the automatic generation of the accelerator you may try to remove all paths and system variable to previous quartus/SOPC/Nios folders. Otherwise you may see error messages like this.

 

The memory copy function example from above gives speed-up factors from 1.8 to 16.3. Substantially higher speed-up is achieved for application where the C2H compiler can build a parallel data flow graph. As examples FFT and FIR application are available from the Altera application notes. Let us have a look at the speed-up and resource used for a 15 TAP FIR filter design next running on the DE2. The following table shows results for a buffer size of 200,000 or 3*106 MACs.

 

 

Nios II/e (debug)

Nios II/e (Release)

Nios II/s (release)

Nios II/f (release)

Time SW

121.88 s

 118.64 s

 3.77 s

850 ms

Time with C2H acceleration

30 ms

30 ms

12.5 ms

12.5 ms

Speed-Up:

4062

3954

301.6

68

 

The whole project with the necessary modification to run on the DE2 can be downloaded here. Here are the related resource data when using the C2H accelerator:

 

Nios II/e (debug)

Nios II/e (Release)

Nios II/s (release)

Nios II/f (release)

LEs

4701

4701

5594

6309

9x9 mult.

16

16

20

20

MHz

74.79

74.79

71.64

144.01

Data Cache

0

0

4K

4K

Instruction Cache

0

0

0

4K

 

 

RELATED PUBLICATIONS*

 

D. González, G. Botella, S. Mookherjeeb, U. Meyer-Bäse, A. Meyer-Bäse; “NIOS II processor-based acceleration of motion compensation techniques” Proc. SPIE Int. Soc. Opt. Eng., Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering IX. April 2011, Vol. 8058, pp. 80581C1-12. http://spie.org/x648.html?product_id=883684

 

U. Meyer-Bäse, G. Botella, E. Castillo, A. García, “Nios II hardware acceleration of the epsilon quadratic sieve algorithm,” Proc. SPIE Int. Soc. Opt. Eng., Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII. April 2010, Vol. 7703, pp. 77030M-1-10. http://spie.org/x648.html?product_id=849883

 

 

Webpage maintained by Dr. Uwe Meyer-Baese email: umeyerbaese@fsu.edu

last updated 8-29-2011